• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    1499010 Message packet switching SIEMENS AG 30 Sept 1975 [30 Sept 1974 30 April 1975 22 May 1975] 39989/75 Heading H4P A message packet switching system comprises storing information signals until a determined number constituting a message block 1 has been received, e.g. from a terminal, and in response to detection of the number applying such a block together with a preceding address signal to a switching device which establishes a connection only during passage of the block. The system allows the reception of data of different rates. A switching device may be a space multiplex exchange and the information block and address signals may be placed into separate stores. The switching devices may comprise a plurality of interconnected exchanges through which information blocks are routed, each exchange storing routing information designating the next exchange in sequence. Alternatively the information may contain addresses indicating individual exchanges on the route, each exchange erasing its own address. An address block may include a "clear down" signal. A receiver, at the remote end, which is not available for any reason can emit an erasing signal to the exchange to which it is connected. Terminal Tn, which may include a subset, is connected through hybrid circuit Gs to a transmitting store comprising Reg 1, 2 and a receiving store Reg 3; Reg 2, 3 may have a capacity of 492 bits and Reg 1 may store 8 sync. bits, 8 address bits, I parity bit and 3 information designating bits. A dialled address is passed through switch Sl and OR gate GO1 into Reg 1, which when full causes switch S1 to reverse allowing information bits to be passed into Reg 2, which when a full detection signal is produced, gives a 1 signal on e input of control circuit Stl. This clocks on its output a the contents of Reg 1 both on a recirculating path including OR gate GO1 and also through GO2 on to a transmitting path into exchange setting device Es. Es checks whether external address path is free and an internal path through exchange Kf is available and if so establishes connection through Kf. When content of St1 has been clocked, output b provides a 1 to monostable circuit MF thus setting a bi-stable circuit in control St2 causing through a, Reg 2 to be clocked out through GO2. When all information bits have been clocked through exchange Kf, the path is released until the next address from Reg 1 is received. Information bits from Kf are received at a remote terminal into a register corresponding to Reg 3, which when a complete block has been received supplies a 1 to input e of St3 setting flipflop FF which closes S2 allowing n pulses from clock generator TGo, as recorded by counter C, to clock out the content of Reg 3 through hybrid circuit Gs to the local terminal. Register St1 stages are then reset for reception of another address by PR. It is possible to arrange transmission and reception consecutively in the same cycle. In Fig. 2 (not shown) messages pass serially through a plurality of exchanges each having an internal control store, e.g. Ccl, Fig. 3 (not shown), co-operating with an address store Es1 through a control store Sp1; signals from the local terminal are therefore received into Ccl and information blocks are not released until a path through exchange Kf1 has been established. The arrangement may work in either of two modes; store Spl may have a number of positions which are addressed and the appropriate setting up information emitted therefrom together with the designation of the next exchange in the chain, or alternatively the local terminal itself may provide a list of exchanges through which information blocks should pass. Each exchange sets up a connection for duration of signals only until they are passed, e.g. into Cc2 et seq.
    公开号:SU858582A3
    申请号:SU752175643
    申请日:1975-09-29
    公开日:1981-08-23
    发明作者:Винтцер Клаус
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    one
    The invention relates to telecommunications and can be used to transmit digital communications signals, which, if necessary, from signal transmitters j, together with the address signal preceding it, which is intended to receive a signal from a particular receiver, in any sequence in time. Q nor through the switching device to the receiver selected using the corresponding address signal.
    A known method of transmitting discrete signals in an asynchronous interconnected address network of communication, in which discrete signals issued by each transmitter, together with the address signal of the called receiver, separate discrete signals, Q, are accumulated separately by the transmitter and, after accumulating a predetermined number, they are issued together with address an address sigial to the connective system, establishing a naval connection with the corresponding called receiver 1 ij.
    It is also known a device for carrying out this method, comprising a transmitter of discrete signals and at-30.
    A discrete signal receiver represented by the subscriber, which is connected to the output of the next switching node Cil through the transfer node. However, the transmission of discrete signals by a known method does not allow an increase in the communication network bandwidth due to the small number of connections through the switching device.
    The purpose of the invention is to increase the capacity of the communication network and provide communication through the interconnecting system formed by a plurality of successive switching nodes.
    This goal is achieved by the fact that in the method of transmitting discrete signals in an asynchronous switched address network, in which it is removable. each transmitter discrete signals together with the previous address signal of the called receiver of discrete signals are pre-accumulated separately by the transmitters and after accumulating a predetermined number they are issued together with the signal with a fresh signal to the connecting system establishing communication with the corresponding called receiver, the connection is established through the connecting system only time equal to the duration of the transfer of the specified number of discrete signals, after which They are immediately interrupted and resumed, again each time only with the same number of subsequent discrete signals with the same address signal.
    In addition, the signals in another embodiment of the method, from the switching node of the transmitter of discrete signals, are transmitted to the switching node of the called receiver of discrete signals so that the corresponding signals of one switching node are sent to the next switching node according to information defining the specific next of those involved in establishing communication with this receiver called switching node.
    In addition, in the third variant of the method, the signals from the transmitter switching node of the discrete signals are transmitted to the switching node of the called receiver according to the addresses specifying specifically the switching nodes of the communication network for transmitting signals to the called receiver, which add to the side of the transmitter specified discrete signals. together with the address indicating the called receiver of discrete signals.
    From the sequence of addresses supplied to the switching node, upon further transmission from the switching node, the addresses designated as such a switching node are excluded.
    In addition, in the sequence of addresses that denote sequentially the switching nodes used to transmit discrete signals, and the called receiver of discrete signals, using the first address in the corresponding switching node, establish a communication field block of this switching node to transmit discrete signals and addresses, and the following after the first address, the addresses and discrete signals, after the time required for the installation of the communication field unit, are transmitted further through the communication field unit of the given node.
    In an apparatus for carrying out the method of the first embodiment, comprising a discrete signal transmitter and a discrete signal receiver, represented by a subscriber, which are connected via an interface to the input and output of the next switching node during transmission, the interface node contains two transmitters for the address signal of the receiver and for a given number of discrete signals and a receiving drive for a given number of discrete signals, the transmission control unit of the accumulators being configured to control tim outputting signals switching node in the presence of a predetermined number of transmitted digital signals, and a control unit receiving a drive vtolnen vozmozhnostk) vschachey control receiver contained in the storage of digital signals to corresponding binary signals to the receiver in the receiver in the presence of a predetermined number of discrete drive signals.
    In addition, the accumulators are made in the form of registers, while the transmitting accumulators are formed by two registers, one of which is intended only for the length of the address signal of the receiver of discrete signals and for signals indicating the type of transmitted discrete signals and / or synchronization signals, and the other register is only for the specified numbers of discrete signals.
    The control units for transmitting and receiving accumulators contain a clock generator, the output of which, via a key, is connected to the control inputs of the corresponding register and to the counter input having a counting capacitance corresponding to the number of signals stored in the corresponding registers, the output of which is connected to the reverse trigger installation input, the output of which is connected to the control input of the key, and the installation input is connected to the interrogative output of the corresponding register.
    A tuning unit is connected to the inputs of the switching node connected to the transmitters of discrete signals and to the outputs of the switching node connected to receivers of the discrete signals.
    In addition, to implement the second variant of the method, in each switching node, an intermediate storage control unit is connected to the corresponding signal input to feed the corresponding switching node signals and output them to the communication field unit only after setting up the communication field unit belonging to the corresponding switching node, moreover, for the corresponding unit of the communication field, a setting unit is provided, with the control input of which the output output of the control unit is connected through the corresponding control accumulator laziness intermediate storage.
    Each intermediate accumulator control unit contains an address accumulator for receiving and storing an address signal of a receiver and a signal accumulator for receiving discrete signals associated with this address signal, and / or an address signal of a transmitter, with the output of address
    The accumulator is the address code of the control unit, the intermediate accumulator.
    In addition, to implement the method of the third option, the input of the communication field unit of each switching node is connected to the output of the corresponding intermediate storage device, and an address register is connected to the input of the corresponding intermediate storage device, which through the control storage device indicates the corresponding block containing the address in the address register. . The communication unit is connected to the setting unit for the corresponding setting of the communication unit of the switching node.
    Figure 1 shows the structural electrical circuit of the device for implementing the proposed method in the first embodiment; Figures 2 and 3 show the structural electrical circuits of the device for implementing the method according to the second embodiment; Fig. 4 shows a structural electrical circuit of a device that realizes the remaining capabilities of the proposed method.
    The device (Fig. 1) contains a transmitter and receiver of discrete signals, represented by subscriber 1, interface 2, switching node 3, tuning block 4, two transmitting accumulators rectified in registers 5 and 6 for the address signal of the receiver and for a given number discrete signals, the receiving drive, made in the form of a register 7, for a given number of discrete signals, blocks 8 and 9 of the control of the transmitting accumulators, block 10 of the control of the receive accumulator, each of the blocks 8, 9 and 10 of the control contains a clock generator 11, Kjno4 12, counter 13, trigger 14, besides branching circuit 15, switch 16, elements SHI 17 and 18, monostable trigger 19, checkout, and amp $ 20.
    The device (Fig. 2) contains transmitters and receivers of discrete signals represented by subscribers 1, Ijj, nodes 2jf, 2 interfaces of the corresponding subscriber 1, i, switching nodes 1 ... 3, each of which consists of an intermediate storage control unit 21 V1N avl dego accumulator 22, block 23 of the field of communication and block 24 settings.
    The BLOCK 21 (FIG. 3) control of the intermediate storage device comprises an address storage 25, a signal storage 26, besides elements AND 27 and 28, a synchronization block 29, a monostable trigger 30, a clock block 31, delay elements 32, 33, 34 and 35, switch 36, synchronization generator 37, clock generator 38, element OR 39,
    The device (Fig. 4) contains transmitters and receivers of discrete signals, represented by subscriber diagrams i and 1 (, nodes 2 and 2 j of the interface of the corresponding subscriber 1, 1 ,, nodes 3 and 3, switching, each of which consists of an intermediate storage control unit 21 , the control accumulator 22, the communication field unit 23, the setting unit 24 and the address register 40.
    ABOUT
    The proposed method is carried out in the following manner.
    Suppose that the transmitter of discrete signals of subscriber 1 started
    S transmission of selective information representing gshres. This selective information, i.e. the bits that make up the address signal go through the separation circuit 15 and the switch
    0 16, which is in the specified position, as well as through the OR element 17 in the register 5 stages provided for this. If register 5 perceives the number of bits of the address signals needed to create a connection with another subscriber station or with a receiver of signals of another subscriber station, This then causes switch 16 to switch. Now the communication signals or bits of the communication signals 0, originating from the transmitter of subscriber 1, are successively stored in the steps of register 6. If the specified number of communication signal bits are accumulated in register 6, then the input of the block
    5 8 signal 1 is received. By this signal, block 8 at its output a delivers the number of pulses corresponding to the number of steps of register 5. It should be noted that this counter
    0 10, contained in block 8, has a counting capacitance corresponding to the number of steps of register 5. When pulses occur at the output of block 8, the bits contained in the steps of register 5 are displaced from this
    5 registers, they successively appear at the output of register 5. These bits of the signals through the element OR 17 are again fed to the input of register 5. This means that register 5 is used as a cyclic memory register. These bits of the signals through the element OR 18 are fed to the input of block 4 settings. This block receives the sign bits data and checks with
    The 5 bits of the address signals, related to these bits of the signals, have a free line passing through this designated output of the switching node 3 and, therefore, to the selected signal reception. If the line is free, then block 4 of the settings finds the still unoccupied switching section and includes this section only for the duration of the transfer.
    5 ks of communication signals. After the bits of the signal are completely crowded out of register 5, no pulses appear at the output of block 8. But now the output to block 8 transmits a signal 1, which acts through a monostable trigger 19 so that the input e of block 9 receives a signal 1 for a completely specified period of time. At the same time, the specified time interval is set to the monostable trigger 19 is in its unstable state. When signal 1 appears at the input of block 9, its trigger 14 is set, as a result of which block 9 will now appear at the output of block 9. At the same time, pulses at output C) of block 9 occur in an amount corresponding to the number of steps of register 6. Accordingly, the counter 13 of the block has a counting capacity corresponding to the number of steps of register 6, After issuing the number of pulses, a certain counting capacity of the counter 13 of block 9 , the bits of the communication signals in register 6 are pushed out of it and through the element OR 18, and also, in this case, after the buffer mode, go through the switched on direct switching node 3 to a certain output. From this output, the data bits of the communication signals arrive at the selected receiver. If all the bits of the communication signals that have just been forced out of the register are transmitted through the switching node 3, then the communication section, which was previously included in it before to transfer the specified bits, is turned off. Accordingly, the direct switching of node 3 is performed again only with the next occurrence of the signals from register 5. This happens when register 6 again accumulates a specified number of communication signal bits. In this case, processes similar to those described proceed. The bits of the communication signals appearing at the output of the switching unit 3, on the line connected to this output, enter the input of the register 7. If the register 7 or the corresponding register in the interface 2 of the selected receiver senses the bits of the communication signals of a specified number, - this number in this case can correspond to the number of steps of register 7, then the input 1 of the corresponding block 10 receives the signal 1, which receives the pulses of the corresponding clock generator 11 at the output of this block. The number of which corresponds to the number of register levels 7, the data of the pulses from the clock generator 11 is terminated. This is done using the counter 13 of block 10, which has a counting capacity corresponding to the number of steps of register 7. With the help of pulses appearing at the output O of block 10, the bits of the communication signals accumulated in register 7 are unloaded from the register and through branching circuit 15 is fed to the selected receiver signals. In this case (not shown in Fig. 1), measures can be taken so that the bits of the communication signals, displaced or shifted from register 7, cyclically one after the other go to the corresponding signal receiver, wherever they are transmitted from the considered signal transmitter. After the bits of the communication signals have been displaced from register 7, this register is again ready to receive the next bits of the communication signals. If the output of the communication signal bits from the transmitter of subscriber 1 is completed, it can recognize the control and return unit 20 and, on the output side, return the steps of register 5 used to receive and store the communication signal bits. The indicated steps of register 5 are therefore recharged with bits of the address signals only when the transmitter of the signals of subscriber 1 is ready to create a new connection with the receiver. An additional register, similar to registers 6 and 7, can be provided and used in the device for carrying out the proposed method (Fig. 1) to avoid loss of information, which, in particular, can occur at relatively high frequencies, transmitting signals from the corresponding subscriber station. station. In addition, the switching node 3 on the input side can be equipped with an intermediate storage device for receiving communication signals transmitted through the switching node 3. Due to this, the resulting signal loss due to the internal blocking of the switching unit 3 can also be eliminated. The clock generators 11, contained in blocks 8.9 and 10 (Fig. 1), transmit, as necessary, pulses with such a following frequency with which the output of the corresponding register receives corresponding bits of communication signals. Nodes 3 switching (figure 2) marked 3, 32, to the switching nodes 3, ... 3 can be as needed connected transmitters and receivers of signals of subscribers 1 in the required quantity. These subscribers 1, 1 through their own nodes 2 mates are connected to the corresponding switching nodes 3. Here we consider only the case when, from subscriber 1, as a transmitter, the signals that go to subscriber 1, which serves as a receiver of signals, are coming out. This means that signals are transmitted only in one direction. The processes considered below proceed in this case in the same way as if signals from an Ig subscriber were transmitted to subscriber 1. Such directional signal transmissions, in particular, play a role in the technology of information transmission. In this case, it is sufficient to transmit signals from one position containing the signal transmitter to the position containing the signal receiver. If from interface 2 signals are output to switching node 3, then these signals are received by the intermediate drive control unit 21 and memorized. The issuance of these signals from the output | block 21 occurs only when block 23 is set up. field of communication This setting is done through setting block 24, which is triggered by the control accumulator 22. To this control accumulator, block 21 receives the address of the signal receiver selected as needed In this case, this is the address of the subscriber 1 or at least 3), switching. Control accumulator 22 is a type of coordination accumulator. The control drive 22 provided at the switching center 3c of the central station 22 | consists of an address-controlled accumulator, in which a separate accumulator cell, as necessary, accumulates the corresponding tuning information about the relation to its field of communication. The positions of the control accumulator 22 are controlled herewith by the addresses of the selected signal receivers. Other switching nodes 3 and subscriber signal receivers 1 can be connected to the outputs of the field 23 of the communication field, which is connected to the switching node 3. In this case, only the switching node 32 on the input side is connected to the output of the communication field unit 23. The structure of this node. The switching completely corresponds to the structure of the switching unit 3. This refers to node 3 at the switching unit, which in this case, through other and correspondingly executed switching nodes 3, must be connected to the input of the unit 2 3 in the communication field of node 2 switching. To the output of block 23 and the field of communication related to the switching node 3c, through the node 2 j. The interface is connected to subscriber 1 j., which serves here as a receiver of signals. Digital communication signals, which can be transmitted from the transmitters as needed in the sequence with the address signal preceding them, indicating the receiver intended to receive the communication signals, are transmitted in any sequence in time through the switching nodes 3 to the receiver of signals indicated by the address signal . At the same time, the communication signals of the corresponding transmitter, prior to their issuance to node 3, kok mutations, are subject to individual (via transmitters) memorization. Only when there is a certain number of communication signals from the respective transmitter, these communication signals together with the address signal designating the selected receiver of signals are output to the switching node 3. With this address signal, this node creates a connection between its input, which passes the address signal and the communication signals following it, and the output of the switching node 3 connected to the selected receiver of signals only for the duration of the transmission of communication signals. In this case, the connection is formed by separate blocks 23., 23, ... 23y, of the communication fields included in the set of interconnected switching network 3 of the communication network. Communication signals emitted from the transmitter of subscriber 1 and collected in a certain amount in node 2 mates are output with their address signal indicating the selected receiver of signals to block 21, which, through control accumulator 22, and block 24. settings control the block 23. The communication field of the switching node 3. That in this block 23. The communication field is the direct switching of the input connected to the output of O.block 21. and, consequently. marking, and the output of block 23. The field of communication leading to another is being considered, the aforementioned switching node 3, only for the duration of the transmission of signals that are stored in block 21 ,. In the case of direct switching of communication field unit 23, these signals are transmitted through it and are rewritten in switching unit 212 3. At this node, block 232. The communication fields are switched directly also only for the transmission of these signals. In the same way, the unit 23 of the communication field of the node 3c is switched directly only to transmit signals, which are memorized in the corresponding block 21. After the direct switching of the corresponding unit 23 ... 23c, its setting is again stopped. New tuning is made only. When receiving the corresponding address signal using block 21, Thus, digital communication signals from the transmitter to the signal receiver are gradually transmitted from one communication node to another. In this case, the communication section is used, which in the individual control accumulators 22 is to some extent remembered, for example, in the form of a configuration information defining the communication field unit 23 only from the input side and from the output side. The control accumulators 22, 1, 22, or 23 C are organized in such a way that they for all communication network switching node 3 about signal receivers contain information about which switching node 3 as the nearest switching node should transmit the sigists on selected receiver. The transmission of communication signals from the transmitter to the signal receiver can additionally be carried out as follows. Before or in addition to the first transmission of communication signals from the switching node 3, to which the transmitter issuing such communication signals is connected, in this case it is node 3, to switching node 3, to which the selected signal receiver is connected, in this case about node 3j, from node 3 to node 3 along with the address signal designating the receiver of subscriber 1 signals, an address signal indicating the transmitter of subscriber 1 is transmitted. Both of these signals are then stored on node 3 containing the selected subscriber receiver Ij. This can be done, for example, in the signal accumulator of the corresponding block 21. If such address signals are compared with corresponding address signals that are transmitted before or in addition to the initial transmission of communication signals that must be transmitted from another transmitter to this signal receiver, relative to which the first specified address signals have already been memorized, due to which the double occupancy of this signal receiver can be relatively simply eliminated. If this comparison of the wide-area signals does not match, this may indicate that the selected receiver has already been occupied, i.e. This moment cannot be used. If it is required, using the scheme in question, to complete the issuance of communication signals from the position of the A-Bonient transmitter Ij to the receiver of subscriber 1, then to node 3, which contains the receiver of subscriber signals, the address signal denoting this receiver can be supplied together with the damping signal and node 3, containing the transmitter subscriber subscriber 1. With this signal, information about the transmitter of subscriber 1 and receiver of subscriber 1 accumulated in the memory node is erased. Consequently, the receiver of the signals of subscriber 1 is again ready to receive communication signals from other transmitters. In this case, the receiver of the signals of the subscriber 1g can still be sent a signal, meaning the end of the supply of communication signals. If desired, the receiver of the signals of subscriber 1 in the considered electric circuit will be turned off or subsequent communication signals from the transmitter of subscriber 1 will not be needed. It is possible from node 3j, containing the receiver of signals of subscriber 1.2. transmit the damping signal, which is still stored on this node 3, ..., to the node 3 containing the signal transmitter. Then, a corresponding indication signal is transmitted from node 3 to the transmitter of subscriber 1. In addition, at node 3 and, containing the receiver of signals of subscriber 1, the accumulated information about the transmitter of subscriber It and the receiver of signals of subscriber 11 is erased. Each block 21 (FIG. 3 contains an address accumulator 25 for receiving and storing an address signal designated by a receiver, for example subscriber 2 (FIG. 2). To this end, the address accumulator 25 is connected by signal input to an output of an AND 28 element, which is connected by one input input e of block 21, another input to the output of monostable trigger 30, which from the input side is controlled by block 29, its input also connected to input e of block 21. The synchronization block 29 outputs output signal 1 when it is in signals fed to its input , recognizes presence In this case, it should be noted that in this case, block-wise or transmitted signals may have the following composition: the first 8 bits form a synchronous word, the next 8 bits form the address of the signal receiver, one bit serves the purpose of parity, The 3 bits serve to indicate the type of signals or, respectively, the bits fed to the signal receiver, and finally the set number of communication signal bits follows. When a synchronous word contained in a specified sequence of signals or bits is recognized, the synchronization unit 29 outputs output signal 1, at the occurrence of which the monostable trigger 30 is moved to its unstable state. The monostable trigger 30 outputs a signal 1 from its output during a period of time during which the bits forming the receiver's address of the snggshov appear at the input of the block 21 of the control of the intermediate storage. As a result, in the range of this time interval, the bits of the address signal are stored in the address accumulator 25. To the input of the intermediate storage control unit 21, the clock unit 31 is also connected with its input. When the corresponding bits occur on the output side, this block outputs clock pulses to the input of the intermediate storage control unit 21. These clock pulses within the time interval during which the monostable trigger 30 is in its stable state are fed through the now-capable element AND 27 to the clock input of the address accumulator 25. The pulses supplied to this clock input cause the bits of the st zi in address storage 25.
    The clock pulses emitted by the TAT unit 31 are also transmitted through a delay element 32 to the clock input of the signal accumulator 26 of the intermediate storage control unit 21. This delay element is calculated so that at the clock input of the signal accumulator 26 the clock pulses occur only at the beginning of the occurrence of communication signal bits. These bits of the communication signals are fed to the signal accumulator 26 to one input, which is connected to the input e of the intermediate storage control unit 21. In this signal accumulator 26, in this case, in addition to vToro, in addition to the bits of the communication signals, an address signal can be recorded designating a signal transmitter from which the bits of the communication signals are derived. This address signal, designation of the signal transmitter, and the atomic signal, designating the receiver, can be specifically rewritten on the switching unit 3 to which the selected signal receiver is connected.
    The outputs of the elements forming the address accumulator 25 are connected to the output o 2 of the intermediate storage control unit 21. This output is connected to the input of the control accumulator 22, which contains the accumulated information for setting up the corresponding unit 23 of the communication field and outputs it via its control.
    In addition, the address accumulator 25 is connected by a signal input through the OR element 39 to the output d of the intermediate storage control unit 21. This output of the intermediate storage control unit 21 is connected to the input of the corresponding communication field unit 23. The output of the signal accumulator 26 is connected to the other input of the element OR 39. In addition, the output of the synchronization generator 37 is connected to another input of the OR 39, which serves to produce a synchronous word corresponding to the received synchronous word. In order to produce such a word synchronously, the synchronization generator 37 is controlled from the input side by corresponding clock pulses. These clock pulses are output by clock generator 38 through delay element 35. To delay element 35, these clock pulses are supplied
    Only at the point in time to which the switch 36, introduced into the connection between the clock generator 38 and the input of the element 35 of the delay, whip. The switch 36 is connected to the control output of the signal accumulator 26 by its actuation input. At this control output, the operation signal, the closing switch 36, arises when the signal bits of the communication signals accumulate in the specified quantity in the signal accumulator 26. The delay time of the delay element 35 is selected in such a way that the adjustment of the corresponding communication field unit 23 is ensured after a given time has passed.
    Clock pulses output from element 35: delays are used not only to control the synchronization generator 37, but also for
    0 control by another delay element 34, to the output of which the clock input of the address accumulator 25 and the input of the delay element 33 are connected. The delay time of element 34 is chosen so that
    5 that the output of the clock pulses from the output of this element begins only when a synchronous word is output from the synchronization generator 37. After that, unloading begins.
    0 bits of the address signal contained in the address accumulator 25. After unloading these bits of the address signal, the signal bits accumulated in the signal accumulator should be unloaded
    5 to 26, namely, by applying the appropriate clock signals to the clock input of the signal accumulator 26. Accordingly, the delay element 33 has a delay time,
    0 which expires when the address signal bits are unloaded from the address memory of the address accumulator 25.
    Thus, in this sequence, the bits of the synchronous word, the bits of the address signal designating the receiver, the bits of the communication signals, and in this case the bits of the address signal designating the transmitter, are received one after the other from the output q of the intermediate control block 21
    0 by the accumulator to the corresponding block 23 of the communication field, connected eg to send these bits of signals. In addition, one bit can be entered into address accumulator 25 for
    5 parity and three bits to indicate the type of communication signal or bit supplied to the signal receiver, so that these bits are also transmitted.
    Regarding the use of x in the wiring diagram (fig.Z) elements
    0 delay follows that they delay the clock pulses supplied to them as needed to equalize the transfer, and in the absence of clock pulses at the corresponding input
    five
    return to their original condition. Regarding the delay element 32, this happens automatically when the bits of the communication signals, and in this case, the bits of the address signal designating the transmitter, are recorded in the signal accumulator 26, for other delay elements this happens because after unloading the corresponding bits of the signals from the signal accumulator 26 36 is open again, and therefore the transmission of clock pulses from the clock generator 38 is interrupted.
    Nodes 3 and 3 (switching (Fig. 4) can be connected to each other or through a number of other switching nodes. A separate number of transmitters and receivers can be connected to separate switching nodes. For example, the transmitter and receiver can be connected , subscriber 1. In this case, only two such subscribers are shown 1. and 1 (-. These subscribers are connected via their own nodes 2 and 2 of the mates to the corresponding switching nodes 3 and 3. The mating nodes 2 can be implemented in the manner shown in FIG. .one.
    Here, only the case is considered when signals from subscriber 1 as transmitter are transmitted to subscriber ly, serving as a receiver of signals. Such signals are digital communication signals. In addition to these communication signals, addresses are issued and transmitted. Thus, in this case, the transmission of signals occurs only in one direction.
    The following processes proceed in the same way as if the communication signals were transmitted from subscriber 1 to subscriber 1. Such directional multi-signal transmissions play a role, in hours; in the information transmission technique. However, in this case, signal transmission from the station containing the signal transmitter to the station containing the signal receiver may be sufficient without using signal transmission between the two stations. in the opposite direction.
    Since the individual switching nodes 3 can be made up in the same way, the structure of only one switching node 3 is further considered. For the definition of mutually corresponding blocks in both shown switching nodes 3, the corresponding symbols are used, the last characters in which (1 or n) denote belonging to one or another node 3, i.e. node 3 or
    node 3v, h
    Switching node 3 (Fig. 4; on each input line contains a delay element 4, for example, which may be a shift register. This shift register has such a number of steps that the maximum number of signal-bits transmitted from the central station may be subjected to intermediate memory. Signals , transmitted from one to another communication network switching node, can have / for example, the following maximum composition: 8 bits form a synchronous word, maximum 10 addresses, of 8 bits each, form addresses of switching nodes, control By transmitting signals, 8 bits form the address of the selected receiver, 1 bit is used for parity, 3 bits are used to indicate the type of communication signals or bits supplied to the receiver, 156 bits form communication signals. In this case, at each switching node have offset shifts with 256 steps to provide signal transmission.
    The signals or bits from the switching node 3j arrive at the delay element 42 through the switch 41 closed in a quiescent state. The trigger input of this switch is connected to the output of a delay element formed by a monostable trigger. According to an embodiment, the delay element can be formed by a clock-controlled counter with a connected decoder, a signal that opens the switch 41, which is outputted during the time when the counter performs the counting process. Such a counting process may use a torn counter by special control, which is carried out from the synchronous word recognition unit 43. At the same time, this block emits the corresponding control signal at the output, when it recognizes a synchronous word in the signals fed to its input. In this case, the bits that make up this synchronous word appear first in the entire sequence of alternating bits.
    The monostable trigger scheme, which is provided in this case as a delay element, after its operation is in an unstable state for such a period of time, when immediately after the specified synchronous word the first address appears among those addresses that sequentially denote switching nodes 3 used for transmitting signals from subscriber transmitter 1; to the receiver signals the subscriber 1 ,. These addresses are placed in front of the transmitted, depending on the needs of the digital communication signals in the signal reception circuit of this transmitter. This can be done in the manner described in connection with FIG. 1 with respect to the address signals. The device (figure 4) follows the following way. Suppose that from node 2, a series of signals or bits are appearing in a series of junctions. The first 8 bits can form a synchronous word, the next 80 bits - 10 addresses denoting the corresponding number of nodes 3 commutations, the next 8 bits can form an address defining the selected signal receiver, the next bi can be a parity bit, the next 3 bits may indicate the type of subsequent communication signals, and finally, the next 156 bits may form digital communication signals. Vita, forming a synchronous word, i.e. in this case, the first 8 bits go through the still closed switch 41 to the delay element 42. In addition, this synchronous word is recognized by the block 43, the recognition of the synchronous word. Thereafter, the switch 41 is opened, and the switch 44 is closed. The 8 bits that now pass, which form the first of all incoming addresses, fall into address register 40. After receiving all the bits of this address from address register 40, switch 44 is opened and switch 41 is closed. All bits that now appear are fed to the Scroll element 42. This delay element senses the signals supplied to it, as necessary, the bits or signals, and remembers them as long as the discharge signals or discharge pulses are applied to it. These pulses are supplied from the clock generator 45 through the switch 46,. The unloading or output of these signals or bits from the delay element 42 occurs when the corresponding block 23 of the communication field is switched directly. The signals or bits emitted from the output of unit 23, the communication fields of switching unit 3 are fed in this case to other similarly arranged and similarly operating switching units 3 until finally the switching circuit containing the following composition is supplied to the input of node 3, switching : the first 8 bits form a synchronous word, the next 8 bits form the address of the selected receiver of the signals of the subscriber Ij, the next bit is the parity bit, the next 3 bits determine the type of subsequent communication signals, and finally the next 156 bits are bits signal in connection with. These bits in the specified sequence appear directly one after the other at the specified input of the 3rdg switching node. Then, on this node, the processes that were described when considering the node 3. switching occur. In the general register 40, the address bits of the selected receiver signals the subscriber 1 c record. Through an appropriate control accumulator 22 and and a setting block 24c, this address contributes to the direct switching of the corresponding block 23 (the communication field, as a result of which the signal bits contained in the delay element 42 are fed to the node 2 and the interface, to which the specified receiver signal of subscriber 11 is connected. Moreover, it happens that the 8 bits of the synchronous word contained in the element 421 are delayed, i.e. are not transmitted if the node 2 and the receiver receiver 1 interfacing do not use the synchronous word. For before The signals from one switching node 3 to another are set up by the communication field unit 23 of the corresponding switching node 3. In this case, the communication setting is made using a button that precedes the communication signals transmitted from the transmitter to the receiver. These addresses, as already noted precede the communication signals from the side of the signal transmitter, namely, in the conjunction node 2 to which this signal transmitter is connected. For this purpose, the conjugation nodes 2 connected to each switching node 3 can be associated with a special accumulator Yelnia circuit which after reception of the address of the selected address of the receiver outputs the switching nodes which are needed when transmitting communication signals from a transmitter by which initsiruets actuation of said accumulator to a selected receiver. This implies that the drive in relation to each controllable receiver of signals contains the addresses of the central stations using the central station to which the drive belongs to transmit signals. The communication field units 23 on the individual switching nodes 3, through which the signals from the transmitter are transmitted to the receiver, are switched, as necessary, directly, but only during the duration of the signal transmission. In relation to the considered ratios, this means that the blocks 23 and 23 of the field of communication are switched directly only as long as the bits of the signals, which are contained respectively in the element 42, are unloaded; | and 42 delays, and are transmitted through the corresponding communication field units 23. In this case, with regard to block 23 and the field of communication, it may happen that 8 bits of the synchronous word contained in element 4: J vi delay do not pass through unit 23y, the field of communication if the node 2 | i of the receiver interface of the signals of subscriber 1 does not use synchronous word. After the data bits of the signals have been transmitted through the corresponding block 23 of the communication field, its switching is again interrupted. Reconfiguration or direct switching of the corresponding unit 23 of the field of communication is carried out only when the corresponding signals are sent to the switching node 3.
    Serial transmission of the communication signals from the transmitter to the receiver may additionally be carried out as follows.
    Before or in addition to the first transmission of communication signals and addresses from the switching node 3, to which a transmitter is connected, issuing these signals (in this case, switching node 3) to switching node 3, to which the selected receiver of signals (in this case, The switching commute from node 3 to node 3 of the C is transmitted in addition to the addresses denoting the switching nodes 3 used for serial transmission of signals from the transmitter to the receiver, and the selected receiver of signals, as well as the address denoting this transmitter signal in subscriber li. This address, along with the address designating the selected receiver of the signals of subscriber 1, is recorded at node 3, the switching to which the receiver of signals of subscriber ly is connected ,. This can be done, for example, in a special storage node of the switching node. If we compare these addresses with the corresponding addresses transmitted before or in addition to the first transmission of communication signals that must be transmitted from other transmitters to the same receiver of subscriber 1, relative to which the specified addresses have already been recorded, then this will relatively simply eliminate double occupancy this receiver signals the subscriber l. If this comparison of the recorded addresses of the transmitter and receiver on the one hand, and the addresses of the receiver and the other transmitter on the other hand, does not match, this can be used as an indication that the selected receiver of signals has already been taken and therefore cannot be .
    If, when using the considered electric circuit, it is required to terminate the signal output from the subscriber’s transmitter 1 to the subscriber’s receiver, then the switching node to which the subscriber’s receiver ly is connected, you can send an address indicating the indicated receiver of the subscriber’s signals 1 together with the damping signal, and namely, the switching node 3, to which the subscriber's transmitter 1 is connected. In addition to this address and the damping signal from the transmitter side, the addresses of the switching nodes 3 are also intended, chennyh for transmitting this signal. Using the address of the receiver of the signals of subscriber 1 and the extinguishing signal, the information accumulated on the switching node 3 relative to the transmitter of subscriber 1 and the receiver of subscriber 1 y, is erased, i.e. the receiver of the signals of subscriber 1 is again ready to receive communication signals from other transmitters. In this case, the receiver of subscriber 1 signals may also be given a key signal, signifying the end of the supply of communication signals.
    If it is required to disconnect the subscriber's signal receiver ly from the specified electrical circuit, or no further communication signals are required from the transmitter of subscriber's 1 signals from node 3, the commutation to which the subscriber's receiver Ij is connected, you can transmit a damping signal along with the address, which is designated as subscriber's 1, which is still stored on this switching node 3j, to the switching node 3 to which the subscriber’s signal transmitter 1 is connected. For this purpose, this dash is prepared, as well as the addresses of the switching nodes 3 involved in the transmission signals from the node memory, switching to node 3 switching, which is connected to the specified transmitter signals. This can be done in the same way that has already been described for the preparation of addresses from the side of signal transmitters. Along with only the considered processes, the switching node to which the receiver of signals of subscriber 1 is connected erases the accumulated information regarding the transmitter of subscriber 1 and receiver of subscriber 1 .
    权利要求:
    Claims (13)
    [1]
    Invention Formula
    1. A method of transmitting discrete signals in an asynchronous switched address network, in which discrete signals sent by each transmitter together with the address signal of the receiver of the discrete signals called before them are pre-accumulated separately by the transmitters and, after accumulating a predetermined number, they are combined with the specified address signal to the interconnecting system that establishes communication with the corresponding called receiver, which is to increase the throughput The ability of the communication network, the connection through the interconnecting system, is established only for a time equal to the duration of the transmission of a given specified number of discrete signals, after which the connection is immediately interrupted and resumed again each time only with the same number of discrete signals. signals with the same address signal.
    [2]
    2. The method according to claim 1, characterized in that, in order to provide communication through a connecting system formed by a plurality of successive switching nodes, signals from the switching node of the sensor transducer of discrete signals are transmitted to the switching node of the called receiving of discrete signals so that that the corresponding signals of one switching node are sent to the next switching node according to the information specifying the specific legacy of those involved in establishing communication with this called receiver of the junction unit.
    [3]
    3. Method POP1, which is also distinguished by the fact that, in order to ensure communication through the interconnecting system, formed by a multitude of switching nodes one after the other, signals from the switching node of the transmitter of the discrete signals are transmitted to the switching node of the called receiver according to the addresses , specifying the communication network switching nodes to be used for transmitting signals to the called receiver, which is added on the transmitter side to the specified discrete signals, together with the address indicating the called discrete signal receiver.
    [4]
    4. The method according to claim 3, characterized in that the addresses assigned to the switching node are excluded from the sequence of addresses supplied to the switching node upon further transmission from the switching node.
    [5]
    5. The method according to claim 4, characterized in that in the sequence of addresses denoting sequentially the switching nodes used to transmit discrete signals and the called receiver of discrete signals, using the first address in the corresponding switching node, install the communication field unit of this switching node for transmitting discrete signals and addresses, and following the first address, the addresses and discrete signals after the time required for installation of the communication field unit are transmitted further through the field communication unit of this switch node atsii.
    [6]
    6. A device for carrying out the method of Claim 1, comprising a discrete signal transmitter and a discrete signal receiver, represented by a subscriber, which are connected via an interface to the input and output of a switching node next in the course of transmission, characterized in that the interface node contains two transmitting accumulator for the address signal of the receiver and for a given number of discrete signals and a receiver for a given number of discrete signals, and the transfer control unit is configured to controlling the signal output to the switching node when there is a specified number of transmitted discrete signals, and the receiving drive control unit is configured to control the output of discrete signals in the receiving drive to the corresponding discrete signal receiver of a specified number of discrete signals.
    [7]
    7. The device according to claim 6, characterized in that the drives are made in the form of registers.
    [8]
    8. The device according to claim 7, characterized in that the transmissions are formed by two registers, one of which is intended only for the address signal of the receiver: discrete signals and for signals indicating the type of transmitted discrete signals and / or synchronization signals, and the other register is only for a given number of discrete signals.
    [9]
    9. The device according to Claims 7 and 8, meaning that the control units of the transmitting and receiving accumulators contain a clock generator, the output of which is connected via a key to the control inputs of the corresponding register and to the counter input having a counting capacity corresponding to the number signals, the maximum stored in the respective registers, the output of which is connected to the input of the reverse installation of the trigger, the installation output of which is connected to the control input of 1 key, and the installation input is connected to the interrogation output of register. .
    [10]
    10. A device in accordance with one of claims 6 to 9, characterized in that a setting unit is connected to the inputs of the switching node connected to discrete signaling transmitters and to the outputs of the switching node connected to receivers of discrete signals.
    [11]
    11. A device in accordance with one of claims 610 for carrying out the method according to claim 2, characterized in that in each switching node a control of an intermediate storage is connected to the corresponding signal input of the signal input for supplying the corresponding
    , the node switching signals and issuing them to the field communication unit only after setting the corresponding node to the switching node of the communication field unit, and for the corresponding field communication unit there is a tuning unit, to the control input of which the output output of the unit is connected to the corresponding input field unit intermediate storage management.
    12. The apparatus of claim 11, wherein each intermediate storage control unit comprises an address accumulator for receiving and storing an address signal of a receiver and a signal accumulator for receiving discrete signals associated with this transmissive signal and / or an address signal. the transmitter signal, the output of the address accumulator being the address output of the intermediate storage control unit.
    [12]
    13. A device according to one of claims 6 to 10 for carrying out the method according to one of claims 3 to 5, characterized in that the input of the communication field unit of each switching node is connected to the output of the corresponding intermediate storage device, and to the input of the corresponding intermediate storage device An address register is connected, which, through the control accumulator, to designate the output address containing the corresponding block in the address register, is connected to the setting unit for the corresponding setting of the switching unit field of the switching node.
    [13]
    Sources of information taken into account in the examination
    1. Lehiwetk F. und Lehvmburq K. Einfuhrung in die Fernschreibvermi11 I ungctechntk, Verlag Erick Herrog (E.H errog and R.OamIn) Goslar 1964, 603-609 (prototype).
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    同族专利:
    公开号 | 公开日
    NL7511461A|1976-04-01|
    LU72648A1|1975-09-29|
    CH599722A5|1978-05-31|
    ATA672875A|1978-12-15|
    FR2286562B1|1980-04-30|
    FR2286562A1|1976-04-23|
    US4061879A|1977-12-06|
    GB1499010A|1978-01-25|
    SE7510959L|1976-05-28|
    IT1042934B|1980-01-30|
    AT351082B|1979-07-10|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    SE318914B|1969-03-18|1969-12-22|Ericsson Telefon Ab L M|
    BE795164A|1972-02-08|1973-05-29|Ericsson Telefon Ab L M|COMMON JUNCTION DOORS CONTROL PROCESS IN A CODED PULSE MODULATION CENTRAL|
    US3890469A|1973-12-04|1975-06-17|Gte Automatic Electric Lab Inc|Time division switching system|US4325147A|1980-06-16|1982-04-13|Minnesota Mining & Manufacturing Co.|Asynchronous multiplex system|
    FR2503497B1|1981-04-03|1988-07-08|Telephonie Ind Commerciale|TEMPORAL TELECOMMUNICATIONS SYSTEM|
    US7831204B1|1981-11-03|2010-11-09|Personalized Media Communications, Llc|Signal processing apparatus and methods|
    USRE47642E1|1981-11-03|2019-10-08|Personalized Media Communications LLC|Signal processing apparatus and methods|
    US4965825A|1981-11-03|1990-10-23|The Personalized Mass Media Corporation|Signal processing apparatus and methods|
    US4488289A|1982-06-25|1984-12-11|At&T Bell Laboratories|Interface facility for a packet switching system|
    US4512016A|1983-02-04|1985-04-16|At&T Information Systems Inc.|Digital communication station signaling control|
    US4512017A|1983-02-04|1985-04-16|At&T Information Systems|Digital dual channel communication terminal|
    FR2600481B1|1986-06-20|1988-08-26|Kalfon Rene|ASYNCHRONOUS SORTING SYSTEM FOR SELF-ROUTING DIGITAL MESSAGES|
    US5187907A|1988-10-31|1993-02-23|Kabushiki Kaisha Toshiba|Interior panel unit for permitting arrangement of cables and devices on room floor|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DE19742446696|DE2446696C3|1974-09-30|1974-09-30|Method and circuit arrangement for the transmission of digital communication signals from signal transmitters to signal receivers via a coupling device|
    DE19752519445|DE2519445C3|1975-04-30|1975-04-30|Method and circuit arrangement for the transmission of digital communication signals from signal transmitters to signal receivers via a coupling device|
    DE19752522759|DE2522759C3|1975-05-22|1975-05-22|Method and circuit arrangement for the transmission of digital communication signals from signal transmitters to signal receivers via a coupling device|
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